description the hcpl-0738 is a dual-channel 15 mbd cmos optocoupler in soic-8 package. the hcpl-0738 optocoupler utilizes the latest cmos ic technol - ogy to achieve out-standing performance with very low power consumption. basic building blocks of hcpl-0738 are high speed leds and cmos detector ics. avago also ofers the same performance in the single channel ver - sion, hcpl-0708. each detector incorporates an integrated photodiode, a high speed transimpedance amplifer, and a voltage comparator with an output driver. f eatures ? 15 ns typical pulse width distortion ? 40 ns maximum propagation delay skew ? 20 ns typical propagation delay ? high speed: 15 mbd ? + 5 v cmos compatibility ? 10 kv/s minimum common mode rejection ? C40 to 100?c temperature range ? safety and regulatory approvals C ul recognized (3750 v rms for 1 minute per ul 1577) C csa component acceptance notice #5. C iec/en/din en 60747-5-2 approved for hcpl-0738 option 060 applications ? pdp (plasma display panel) ? digital feld bus isolation: devicenet, sds, profbus ? multiplexed data transmission ? computer peripheral interface ? microprocessor system interface ? dc/dc converter caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. truth table led v o , output off h on l note: a 0.1 f bypass capacitor must be con - nected between pins 5 and 8. functional diagram 8 7 6 1 3 5 2 4 anode 1 cathode 1 cathode 2 anode 2 v dd v o 2 gnd led off on truth table v o 1 v o , output h l hcpl-0738 high speed cmos optocoupler data sheet lead (pb) free rohs 6 fully compliant rohs 6 fully compliant options available; -xxxe denotes a lead-free product
package outline drawing hcpl-0738 outline drawing (small outline so-8 package) selection guide small outline so-8 hcpl-0738 xx x yww 8 7 6 5 4 3 2 1 pi n one 7 5.994 0.203 (0.236 0.008) 3.937 0.127 (0.155 0.005) 0.405 0.076 (0.015 0.003) 1.270 (0.050) bsc *5.080 0.127 (0.205 0.005) 3.175 0.127 (0.125 0.005) 1.524 (0.060) 45 x 0.432 (0.017) 0.228 0.025 (0.009 0.001) 0.202 0.102 (0.008 0.004) type number (last 3 digits ) date code *total package length (inclusive of mold flash ) 5.207 0.254 (0.205 0.010) dimensions in millimeters and (inches) . lead coplanarity = 0.10 mm (0.004 inches) max. note: floating lead protrusion is 0.15 mm (6 mils) max. 0.305 (0.012) min. 0 - 7 7.49 (0.295) 1.9 (0.075) 0.64 (0.025) land pattern recommendation ordering information hcpl-0738 is ul recognized with 3750 vrms for 1 minute per ul1577. part number option package surface mount gull wing tape & reel ul 5000 vrms/ 1 minute rating iec/en/din en 60747-5-2 quantity rohs compliant non rohs compliant hcpl-0738 -000e no option so-8 x 100 per tube -500e -500 x x 1500 per reel -060e -060 x x 100 per tube to order, choose a part number from the part number column and combine with the desired option from the op - tion column to form an order entry. example 1: HCPL-0738-500E to order product of small outline so-8 package in tape and reel packaging in rohs compliant. example 2: hcpl-0738 to order product of small outline so-8 package in tube packaging and non rohs compliant. option datasheets are available. contact your avago sales representative or authorized distributor for information.
3 solder refow temperature profle 0 time (seconds) temperature (c) 200 100 50 150 100 200 250 300 0 30 sec. 50 sec. 30 sec. 160c 140c 150c peak temp . 245c peak temp . 240c peak temp. 230c soldering tim e 200c preheating tim e 150c, 90 + 30 sec. 2.5c 0.5c/sec. 3c + 1c/?0.5c tight typical loos e room temperature preheating rate 3c + 1c/?0.5c/sec. reflow heating rate 2.5c 0.5c/sec. recommended pb-free ir profle 217 c ramp-d ow n 6 c/sec. max. ramp-u p 3 c/sec . max . 150 - 200 c 260 +0/-5 c t 25 c to pea k 60 to 150 sec. 20-40 sec. time w ithin 5 c of ac tu al peak tempera t ure t p t s prehea t 60 to 180 sec. t l t l t smax t smin 25 t p tim e tempera ture no tes: the time fr om 25 c to peak tempera ture = 8 minutes max. t smax = 200 c, t smin = 150 c note: non-halide fux should be used. note: non-halide fux should be used.
all avago data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are needed as a starting point for the equip - ment designer when determining the circuit insulation requirements. however, once mounted on a printed circuit board, minimum creepage and clearance require - ments must be met as specifed for individual equipment standards. for creepage, the shortest distance path along regulatory information the hcpl-0738 has been approved by the following organizations: ul recognized under ul 1577, component recognition program, file e55361. csa approved under csa component acceptance notice #5, file ca88324. iec/en/din en 60747-5-2 approved under: iec 60747-5-2:1997 + a1:2002 en 60747-5-2:2001 + a1:2002 din en 60747-5-2 (vde 0884 teil 2):2003-01 (option 060 only) the surface of a printed circuit board between the solder fllets of the input and output leads must be considered. there are recommended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level. insulation and safety related specifcations (approval pending) parameter symbol value units conditions minimum external air gap l(i01) .9 mm measured from input terminals to output terminals, (clearance) shortest distance through air. minimum external tracking l(i0 ) .8 mm measured from input terminals to output terminals, (creepage) shortest distance path along body. minimum internal plastic gap 0.08 mm insulation thickness between emitter and detector; also (internal clearance) known as distance through insulation. tracking resistance cti 175 volts din iec 11/vde 0303 part 1 (comparative tracking index) isolation group iiia material group (din vde 0110, 1/89, table 1) absolute maximum ratings parameter symbol minimum maximum units storage temperature t s C55 15 ?c ambient operating temperature t a C0 100 ?c supply voltage v dd 0 6.0 volts output voltage v o C0.5 v dd + 0.5 volts average forward input current i f 0 ma average output current i o ma lead solder temperature 60?c for 10 seconds, 1.6 mm below seating plane solder refow temperature profle see solder refow thermal profle section recommended operating conditions parameter symbol minimum maximum units ambient operating temperature t a C0 100 ?c supply voltages v dd .5 5.5 v input current (on) i f 10 16 ma
5 switching specifcations over recommended temperature (t a = C0?c to +100?c) and .5 v v dd 5.5 v. all typical specifcations are at t a = 5?c, v dd = +5 v. parameter symbol min. typ. max. units test conditions fig. notes propagation delay time t phl 0 35 60 ns i f = 1 ma, c l = 15 pf 5 1 to logic low output cmos signal levels propagation delay time t plh 11 0 60 ns i f = 1 ma, c l = 15 pf 5 1 to logic high output cmos signal levels pulse width pw 100 ns pulse width distortion |pwd| 0 15 30 ns i f = 1 ma, c l = 15 pf 5 cmos signal levels propagation delay skew t psk 0 ns i f = 1 ma, c l = 15 pf 3 cmos signal levels output rise time t r 0 ns i f = 0 ma, c l = 15 pf (10% C 90%) cmos signal levels output fall time t f 5 ns i f = 1 ma, c l = 15 pf (90% C 10%) cmos signal levels common mode transient |cm h | 10 15 kv/s v cm = 1000 v, t a = 5?c, immunity at logic high output i f = 0 ma common mode transient |cm l | 10 15 kv/s v cm = 1000 v, t a = 5?c, 5 immunity at logic low output i f = 1 ma electrical specifcations over recommended temperature (t a = C0?c to +100?c) and .5 v v dd 5.5 v. all typical specifcations are at t a = 5?c, v dd = +5 v. parameter symbol min. typ. max. units test conditions fig. notes input forward voltage v f 1.3 1.5 1.8 v i f = 1 ma 1 input reverse breakdown bv r 5 v i r = 10 a voltage logic high output voltage v oh .0 5 v i f = 0, i o = C0 a logic low output voltage v ol 0.01 0.1 v i f = 1 ma, i o = 0 a input threshold current i th .5 8. ma i ol = 0 a logic low output supply i ddl 10 18.0 ma i f = 1 ma current logic high output supply i ddh 8 15.0 ma i f = 0 ma 3 current
6 package characteristics all typicals at t a = 5?c. parameter symbol min. typ. max. units test conditions input-output insulation i i-o 1 a 5% rh, t = 5 s v i-o = 3 kv dc, t a = 5?c input-output momentary v iso 3750 v rms rh 50%, t = 1 min., withstand voltage t a = 5?c input-output resistance r i-o 10 1 ? v i-o = 500 v dc input-output capacitance c i-o 0.6 pf f = 1 mhz, t a = 5?c notes: 1. t phl propagation delay is measured from the 50% level on the rising edge of the input pulse to the 2.5 v level of the falling edge of the v o signal. t plh propagation delay is measured from the 50% level on the falling edge of the input pulse to the 2.5 v level of the rising edge of the v o signal. 2. pwd is defned as |t phl - t plh |. 3. t psk is equal to the magnitude of the worst case diference in t phl and/or t plh that will be seen between units at any given temperature within the recommended operating conditions. 4. cm h is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state. 5. cm l is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state. figure 1. typical input diode forward characteristic. figure 2. typical input threshold current vs. tempera - ture. figure 3. typical logic high o/p supply current vs. temperature. figure 4. typical logic low o/p supply current vs. temperature. figure 5. typical switching speed vs. pulse input cur - rent. v f ? forward voltage ? v 100 10 0.1 0.01 1.1 1.2 1.3 1.4 i f ? forward current ? ma 1.6 1.5 1.0 0.001 1000 i f v f + t a = 25c ? i th ? input threshold current ? ma -40 0 t a ? temperature ? c 100 7 1 60 0 2 0 8 5 3 4 i th 1 i th 2 -20 40 80 2 6 v dd = 5.0 v i ol = 20 a tp ? propagation delay ? ns 5 0 i f ? pulse input current ? ma 14 45 hcpl-0738 fig 5 10 11 7 9 50 30 20 25 5 40 6 8 10 12 13 15 35 v dd = 5.0 v t a = 25 c t phl ch 1 t phl ch 2 t plh ch 2 pw d ch 2 pw d ch 1 t plh ch 1 -40 t a ? temperature ? c 100 60 0 2 0 i ddh -20 40 80 i ddh ? logic high output supply current ? ma 6.0 9.5 7.0 10.0 8.5 7.5 8.0 6.5 9.0 v dd = 5.0 v -40 t a ? temperature ? c 100 60 0 2 0 i ddl -20 40 80 9.6 11.4 10.0 11.6 10.8 10.4 10.6 9.8 11.2 i ddl ? logic low supply current ? ma 11.0 10.2 v dd = 5.0 v
7 propagation delay, pulse-width distortion, and propagation delay skew propagation delay is a fgure of merit which describes how quickly a logic signal propagates through a system. the propagation delay from low to high (t plh ) is the amount of time required for an input signal to propagate to the output, causing the output to change from low to high. similarly, the propagation delay from high to low (t phl ) is the amount of time required for the in - put signal to propagate to the output, causing the output to change from high to low (see figure 7). pulse-width distortion (pwd) results when t plh and t phl difer in value. pwd is defned as the diference between t plh and t phl and often determines the maxi- mum data rate capability of a transmission system. pwd figure 6. recommended printed circuit board layout. application information bypassing and pc board layout the hcpl-0738 optocoupler is extremely easy to use. no external interface circuitry is required because the hcpl- 0738 uses high-speed cmos ic technology allowing cmos logic to be connected directly to the inputs and outputs. can be expressed in percent by dividing the pwd (in ns) by the minimum pulse width (in ns) being transmitted. typically, pwd on the order of 20-30% of the minimum pulse width is tolerable; the exact fgure depends on the particular application (rs232, rs422, t-1, etc.). propagation delay skew, t psk , is an important parameter to con-sider in parallel data applications where synchro - nization of signals on parallel data lines is a concern. if the parallel data is being sent through a group of op - tocouplers, diferences in propagation delays will cause the data to arrive at the outputs of the optocouplers at diferent times. if this diference in propagation delays is large enough, it will determine the maximum rate at which parallel data can be sent through the optocouplers. as shown in figure 6, the only external component required for proper operation is the bypass capacitor. capacitor values should be between 0.01 f and 0.1 f. for each capacitor, the total lead length between both ends of the capacitor and the power-supply pins should not exceed 20 mm. 7 5 6 8 2 3 4 1 gnd 2 c v dd gnd 1 xxx yw w v o 2 v o 1 i f1 gnd 1 i f2
8 propagation delay skew is defned as the diference be - tween the minimum and maximum propagation delays, either t plh or t phl , for any given group of optocouplers which are operating under the same conditions (i.e., the same supply voltage, output load, and operating temperature). as illustrated in figure 8, if the inputs of a group of optocouplers are switched either on or off at the same time, t psk is the diference between the shortest propagation delay, either t plh or t phl , and the longest propagation delay, either t plh or t phl . as mentioned earlier, t psk can determine the maximum parallel data transmission rate. figure 8 is the timing dia - gram of a typical parallel data application with both the clock and the data lines being sent through optocouplers. the fgure shows data and clock signals at the inputs and outputs of the optocouplers. to obtain the maximum data transmission rate, both edges of the clock signal are being used to clock the data; if only one edge were used, the clock signal would need to be twice as fast. propagation delay skew repre-sents the uncertainty of where an edge might be after being sent through an optocoupler. figure 7 shows that there will be uncertainty in both the data and the clock lines. it is im - portant that these two areas of uncertainty not overlap, otherwise the clock signal might arrive before all of the data outputs have settled, or some of the data outputs may start to change before the clock signal has arrived. from these considerations, the absolute minimum pulse width that can be sent through optocouplers in a parallel application is twice t psk . a cautious design should use a slightly longer pulse width to ensure that any additional un - certainty in the rest of the circuit does not cause a problem. the t psk specifed optocouplers ofer the advantages of guaranteed specifcations for propagation delays, pulse- width distortion and propagation delay skew over the recommended temperature, and power supply ranges. figure 7. propagation delay skew waveform. figure 8. parallel data transmission example. 50% 50% t ps k i f v o i f v o 2.5 v, cmos 2.5 v, cmos data inputs clock data outputs clock t ps k t psk 8 for product information and a complete list of distributors, please go to our website: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies limited in the united states and other countries. data subject to change. copyright ? 007 avago technologies limited. all rights reserved. av0 -0878en january 8, 008
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